Recently-developed processor-based computing systems, with high bandwidth, deeply-pipelined, split-transaction bus structures, allow for multiple concurrent transactions between the I/O, memory and processor (CPU) subsystems. In order to take advantage of the higher performance such systems can provide while maintaining data correctness throughout the system, proper ordering of the various transactions must be ensured so that I/O system transactions to memory are executed in the proper sequence as compared with CPU transactions to the same memory and CPU transactions to the I/O system.
To illustrate the potential problems that improper transaction ordering can cause, consider, as an example, the following sequence of transactions: (1) a processor initiates a data write to I/O; (2) the processor then initiates a write of a semaphore, or status bit, to memory, indicating that the I/O data write has occurred; and (3) an I/O device initiates a read to the memory to fetch the semaphore to determine whether the write from the processor to I/O has been completed. If the first transaction, i.e., the processor write to I/O, is placed in a queue containing transactions destined for I/O, and if the delay in execution of the write transaction (i.e., the delay in the time it takes the write to reach the head of the queue and thus be processed) is sufficiently long, then it is possible that transactions (2) and (3) could be executed before transaction (1), i.e., the processor write of the semaphore to memory and the subsequent I/O read of memory to check the value of the semaphore could occur prior to the processor write to I/O. If so, then the I/O device inquiring into the semaphore will receive erroneous status information indicating that the data write to I/O has been completed, when it has not.
To avoid this erroneous potential result, in prior art processor-based computing systems, placement of any memory reads initiated by I/O into the "inbound" transaction queue, i.e., the queue containing transactions initiated by I/O and targeted at memory, is delayed until all write transactions in the "outbound" queue, i.e., the queue containing transactions initiated by the processor and targeted at I/O, are completed. This is necessary in such systems because there is no way to determine whether any of the as-yet-unexecuted outbound writes are "related" to the inbound read (i.e., may affect the accuracy of what is about to be read). Thus, in prior art systems, the assumption must be made that the outbound writes are potentially related to the inbound read, and thus the read cannot be performed until any previously-initiated writes are completed. This ensures that the result returned from the read accurately represent the current state of affairs in the system.
Delaying execution of the inbound read, however, diminishes the concurrence capability of these advanced processor-based computing systems. If placement of the read transaction into the inbound queue must be delayed until all outbound writes are completed, then placement in the inbound queue of any other transactions that I/O attempts to initiate following the read must also be delayed. Concurrence is further diminished in many prior art systems in that, while the inbound read transaction is being processed, no further outbound transactions can be placed into the outbound queue.
In addition to proper transaction ordering, cache coherence must also be taken into account in an I/O to memory system interface. Because the memory locations that will be read from or written to by an I/O device typically will be cached in the computing system's processor or processors, it is necessary that the I/O transactions targeted at memory be made visible to the cache(s) inside the processor(s), so that system-wide cache coherence can be maintained.
It is desired, then, to provide a transaction ordering capability for a processor-based computing system which allows for greater transaction concurrence than prior art computing systems - - - thereby providing higher bandwidth transaction processing - - - while maintaining data correctness and cache coherence within the computing system.